VHDL Programming

182 Chapter Seven no other mapping needs to take place. The default mapping causes the ports to match. What happens when the com ...

Configurations 183 END FOR; END FOR; END decode_map_con; The port map clause maps the port names of the component declara- tions ...

184 Chapter Seven END behave; CONFIGURATION and2con OF and2 IS FOR behave END FOR; END and2con; Two of these can be connected wi ...

Configurations 185 CONFIGURATION decode_map_con OF decode IS FOR structural FOR ALL : inv USE ENTITY WORK.inv(behave); END FOR; ...

186 Chapter Seven configuration sections. If no overriding values are present, the default values are used; but if a value is ma ...

Configurations 187 a new function,calc_delay, which is used to retrieve the proper delay value from the delay table, depending o ...

188 Chapter Seven After the entities and architectures for the gates have been defined, configurations that provide specific val ...

Configurations 189 GENERIC MAP( mode => minimum, delay_tab => ((1.3 ns, 1.9 ns), delay_tab => ((2.1 ns, 2.9 ns), delay_ ...

190 Chapter Seven generics have been mapped in the architecture. The configuration can be specified as shown in the following: C ...

Configurations 191 to map the delays back to the model. Modifying the architecture involves changing the values in all of the ge ...

192 Chapter Seven END inv_gen1; ------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENT ...

Configurations 193 SIGNAL nota, notb : std_logic; BEGIN I1 : inv PORT MAP( a, nota); I2 : inv PORT MAP( b, notb); AN1 : and3 POR ...

194 Chapter Seven FOR AN2 : and3 USE ENTITY WORK.and3(and3_gen1) GENERIC MAP( int_rise => 2.2 ns, GENERIC MAP( int_fall => ...

Configurations 195 The information in this section on generics can be summarized by the charts shown in Figures 7-3 and 7-4. (Th ...

196 Chapter Seven board-socket-chip analogy. (This analogy was originally presented to me by Dr. Alec Stanculescu.) In this anal ...

Configurations 197 ENTITY board IS GENERIC (qdelay, qbdelay : time); PORT( clk, reset, data_in : IN std_logic; PORT( data_out : ...

198 Chapter Seven ation and the actual entity, then a mapping between the socket (compo- nent instantiation) and the chip (actua ...

Configurations 199 FOR U1,U2: dff USE WORK.dff(behave) GENERIC MAP( q_out => g1, qb_out => g2) PORT MAP( preset => grou ...

200 Chapter Seven R2 : int_reg PORT MAP( data(1), clock, data(1)); R3 : int_reg PORT MAP( data(2), clock, data(2)); R4 : int_reg ...

Configurations 201 FOR shifter FOR A1 : alu USE CONFIGURATION WORK.alu_con; END FOR; FOR shift_reg FOR R1 : int_reg USE CONFIGUR ...