VHDL Programming

In Figure 12-7, location 48 is all zeroes. In Figure 12-8, location 48 is no longer all zeroes, but has the first value from the ...

CHAPTER 1 Basic Concepts This chapter answers the question,“What are abstract data types?”The idea of using well-designed abstra ...

304 Chapter Thirteen Reg0 Reg1 Reg2 Reg3 Reg7 Regsel ProgCnt AddrReg Addr(15:0) Data(15:0) ALU Control Ready R/W VMA Shift ...

CPU: Synthesis Description 305 component reg port( a : in bit16; port( clk : in std_logic; port( q : out bit16); end component; ...

306 Chapter Thirteen port( sel : in t_comp; port( compout : out std_logic); end component; signal opdata, aluout, shiftout, inst ...

CPU: Synthesis Description 307 c sel ab ALU Figure 13-2 ALU Interface. Inputs aand bare the two input busses upon which the ALU ...

308 Chapter Thirteen Sel Input Operation 0000 C = A 0001 C = A AND B 0010 C = A OR B 0011 C = NOT A 0100 C = A XOR B 0101 C = A ...

CPU: Synthesis Description 309 Comp The next component described is the comparator entity comp. This entity compares two values ...

310 Chapter Thirteen use work.cpu_lib.all; entity comp is port( a, b : in bit16; sel : in t_comp; compout : out std_logic); end ...

CPU: Synthesis Description 311 The comparator consists of a large casestatement where each branch of the casestatement contains ...

312 Chapter Thirteen Reset ProgCntrWr ProgCntrRd AddrRegWr AddrRegRd OutRegWr OutRegRd ShiftSel AluSel CompSel OpRegRd OpRegWr I ...

CPU: Synthesis Description 313 vma <= ‘ 0 ’; case current_state is when reset1 => aluSel <= zero after 1 ns; shiftSel & ...

314 Chapter Thirteen next_state <= store2; when “ 00011 ” => ----- move regSel <= instrReg(5 downto 3); regRd <= ‘ 1 ...

CPU: Synthesis Description 315 next_state <= incPc; when store2 => regSel <= instrReg(2 downto 0); regRd <= ‘ 1 ’; a ...

316 Chapter Thirteen next_state <= loadI5; when loadI5 => vma <= ‘ 1 ’; rw <= ‘ 0 ’; next_state <= loadI6; when l ...

CPU: Synthesis Description 317 next_state <= bgtI3; when bgtI3 => opRegRd <= ‘ 1 ’; regSel <= instrReg(2 downto 0); ...

318 Chapter Thirteen next_state <= loadPc; else next_state <= bgtI10; end if; when inc2 => regSel <= instrReg(2 down ...

CPU: Synthesis Description 319 progcntrRd <= ‘ 1 ’; alusel <= inc; shiftsel <= shftpass; outregWr <= ‘ 1 ’; next_sta ...

320 Chapter Thirteen copy the next state to the current state. The next state transitions occur on rising edges of the clock inp ...

CPU: Synthesis Description 321 The resetof the description for the state machine contains the state transitions for the rest of ...