VHDL Programming

RETURN result; END “nand”; ------------------------------------------------------- -- or --------------------------------------- ...

IF ( l’LENGTH /= r’LENGTH ) THEN ASSERT FALSE REPORT “arguments of overloaded ‘nor’ operator are not of the same length” SEVERIT ...

END “xor”; ------------------------------------------------------- FUNCTION “xor” ( l,r : std_ulogic_vector ) RETURN std_ulogic_ ...

-- ------------------------------------------------------- -- function “xnor” ( l,r : std_ulogic_vector ) return std_ulogic_vect ...

std_ulogic’HIGH) OF X01Z; TYPE logic_ux01_table IS ARRAY (std_ulogic’LOW TO std_ulogic’HIGH) OF UX01; -------------------------- ...

-- returns : ux01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_ ...

FOR i IN result’RANGE LOOP CASE sv(i) IS WHEN ‘ 0 ’ | ‘L’ => result(i) := ‘ 0 ’; WHEN ‘ 1 ’ | ‘H’ => result(i) := ‘ 1 ’; W ...

WHEN ‘ 0 ’ => result(i) := ‘ 0 ’; WHEN ‘ 1 ’ => result(i) := ‘ 1 ’; END CASE; END LOOP; RETURN result; END; -------------- ...

BEGIN FOR i IN result’RANGE LOOP CASE bv(i) IS WHEN ‘ 0 ’ => result(i) := ‘ 0 ’; WHEN ‘ 1 ’ => result(i) := ‘ 1 ’; END CAS ...

FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS BEGIN RETURN (cvt_to_x01z(s)); END; ----------------------------------------- ...

ALIAS sv : std_ulogic_vector ( 1 TO s’LENGTH ) IS s; VARIABLE result : std_ulogic_vector ( 1 TO s’LENGTH ); BEGIN FOR i IN resul ...

BEGIN RETURN (s’EVENT AND (To_X01(s) = ‘ 1 ’) AND (To_X01(s’LAST_VALUE) = ‘ 0 ’)); END; FUNCTION falling_edge (SIGNAL s : std_ul ...

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Appendix B VHDL Reference Tables This appendix focuses on tables of information that are useful when writ- ing VHDL descriptions ...

436 Appendix B: VHDL Reference Tables Table B-1 Continued. Statement or Clause Example(s) Component Declaration COMPONENT compon ...

Appendix B: VHDL Reference Tables 437 Table B-1 Statement or Clause Example(s) Function Declaration FUNCTION function_name (para ...

438 Appendix B: VHDL Reference Tables Table B-1 Continued. Statement or Clause Example(s) Library Declaration LIBRARY library_na ...

Appendix B: VHDL Reference Tables 439 Table B-1 Statement or Clause Example(s) Process Statement PROCESS (signal1, signal2, sign ...

440 Appendix B: VHDL Reference Tables Table B-2 Attribute Explanation Examples T’BASE Returns the base type of NATURAL’BASE retu ...

Appendix B: VHDL Reference Tables 441 All of the next examples apply to the following declaration: TYPE a_type IS ARRAY(0 TO 3, ...