VHDL Programming

22 Chapter Two AB Delay = 20 ns A B 0 10 20 30 40 Figure 2-5 Transport Delay Buffer Waveforms. propagation. At time 10 nanosecon ...

Behavioral Modeling 23 ARCHITECTURE buf OF buf IS BEGIN b <= a AFTER 20 ns; END buf; Transport Delay Model Following is an ex ...

24 Chapter Two D CLK Q QB DFF A Clock C D B E F Figure 2-6 Simulation Delta Circuit. To use delta delay, all of the circuit comp ...

Behavioral Modeling 25 AND First NAND First evaluate inverter evaluate inverter B <= 1 B <= 1 evaluate AND (C = 1) evaluat ...

26 Chapter Two Time Delta Activity 10 ns (1) A <= 0 evaluate inverter (2) B <= 1 evaluate AND evaluate NAND (3) D <= 1 ...

Behavioral Modeling 27 ENTITY reg IS PORT( a, clock : in bit PORT( d : out bit); END reg; ARCHITECTURE test OF reg IS SIGNAL b, ...

28 Chapter Two signal assignment statement creates a driver for signal a. The first state- ment creates a driver that contains t ...

Behavioral Modeling 29 ARCHITECTURE better OF mux IS BEGIN q <= i0 WHEN a = ‘ 0 ’ AND b = ‘ 0 ’ ELSE i1 WHEN a = ‘ 1 ’ AND b ...

30 Chapter Two delays, as well as the loading that the device has on its output. With this information, the model can correctly ...

Behavioral Modeling 31 to out1. In the same way, component U2is mapped to signals inc, ind, and out2. Generic riseof instance U1 ...

32 Chapter Two to logically group areas of the model. The analogy with a typical Schematic Entry system is a schematic sheet. In ...

Behavioral Modeling 33 END BLOCK REG8; END cpu_blk; Entity cpuis the outermost entity declaration of this model. (This is not a ...

34 Chapter Two END BLOCK BLK1; In this example, signal qbusis declared in two blocks. The interesting feature of this model is t ...

Behavioral Modeling 35 USE WORK.math.ALL; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY cpu IS PORT( clk, interrupt : IN std ...

36 Chapter Two some more of the details: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY latch IS PORT( d, clk : IN std_logic; ...

Behavioral Modeling 37 new signal is implicitly declared in the block whenever a block has a guard expression. This signal is ca ...

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Chapter 3 Sequential Processing In Chapter 2, we examined behavioral modeling using concurrent statements. We discussed concurre ...

40 Chapter Three Process Statement In an architecture for an entity, all statements are concurrent. So where do sequential state ...

Sequential Processing 41 PORT( a, b : IN std_logic; PORT( c : OUT std_logic); END nand2; ARCHITECTURE nand2 OF nand2 IS BEGIN PR ...