FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

bb "0000000110110000", "0000001100110000", "0000011000110000", "0000110000110000", "0001100000110000", "0001111111111000", "0000 ...

cc "0000000000000000", "0000000000000000", "0000111111111000", "0000100000011000", "0000000000011000", "0000000000110000", "0000 ...

dd "0000000000001100", "0000000000001100", "0000000000001100", "0000000000001100", "0011000000001100", "0001100000011000", "0000 ...

ee --caracterul----- 0 1 2 3 4 5 6 7 8 9. --pozitia-------- 0 1 2 3 4 5 6 7 8 9 10 11 entity ROM_extract_pixel is Port ( clk : i ...

ff data(3) WHEN "1100", data(2) WHEN "1101", data(1) WHEN "1110", data(0) WHEN "1111", 'X' WHEN OTHERS; x(8 downto 4) <= adrC ...

gg process(clkb) begin if(clkb'event and clkb = '1')then if(enb = '1') then do <= RAM(conv_integer(unsigned(addrb))); end if; ...

hh helloworld.c #include "xparameters.h" #include "xgpio.h" #include "xil_printf.h" #define LED 0x01 / Assumes bit 0 of GPIO is ...

ii use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity demo is Port ( CLK100MHZ : in STD_LOGIC; rst: in STD_LOGIC; ...

jj C : out STD_LOGIC_VECTOR (6 downto 0)); end component; component shift_reg is Generic(number_of_FF: integer := 16); Port ( cl ...

kk signal uart_tx_done: STD_LOGIC := '0'; signal vga_en_q: STD_LOGIC := '0'; signal ssd_display_counter: STD_LOGIC_VECTOR (31 do ...

ll adrCol => HAddr(3 downto 0), q => ROM_extract_pixel_q ); vga_patt: VGA_pattern Port Map( clk => clk65MHz, R => R_ ...

mm led_ctrl: process(clk65MHz) begin if rising_edge(clk65MHz) then if rst = '1' then shift_reg_load <= '1'; led_switch_counte ...

nn end process; uut: uart_tx Generic Map( system_clock => 65000000, baud_rate => 9600) Port Map( clk => clk65MHz, tx =& ...

oo set_property PACKAGE_PIN N3 [get_ports {LED[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] set_property PACKAGE ...

pp set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] set_propert ...

qq set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] set_property PACKAGE_PIN R2 [get_ports {sw[15]}] set_property IOSTANDAR ...

rr end process; end generate data_in_gen; end generate reg_generated; end Behavioral; pkg_demo.vhd library IEEE; use IEEE.STD_LO ...

ss led_shift_counter <= led_shift_counter + '1'; shift_reg_ce <= '0'; else led_shift_counter <= x"0000_0000"; shift_reg ...

tt function add_f (A,B: data_type) return data_type is variable m: data_type; begin m:=a + b; return m; end add_f; procedure sub ...

uu cnt_pgoc: process(clk) begin if rising_edge(clk) then if cnt_test = x"01" then a <= "010" after 1ns; b <= "011" after 1 ...