FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

h constant clk_divider: integer := system_clock / baud_rate; signal tx_clk_cnt: integer range 0 to clk_divider := 0; signal tx_c ...

i tx <= '0'; when S_b0 => tx <= data_buf(0); st <= S_b1; when S_b1 => tx <= data_buf(1); st <= S_b2; when S ...

j system_clock: integer; baud_rate: integer ); port ( RX : in std_logic; -- Receiver input. DATA : out std_logic_vector(7 downto ...

else cnt_sample <= 0; cnt_bit <= 0; end if; end if; end process; process(clk) begin if(rising_edge(clk)) then if(cnt_bit = ...

l C : out STD_LOGIC_VECTOR (7 downto 0)); end SSD_CTRL; architecture Behavioral of SSD_CTRL is constant max_sweeping_value: std_ ...

m digit_select(i + 1) <= digit_select(i); end loop; end if; end if; end process; digit_display: process(clk) begin if rising_ ...

n cb <= '0'; cc <= '0'; cd <= '1'; ce <= '1'; cf <= '0'; cg <= '0'; elsif data(i 4 + 3 downto i 4) = x"5" th ...

o cg <= '0'; else ca <= '1'; cb <= '1'; cc <= '1'; cd <= '1'; ce <= '1'; cf <= '1'; cg <= '1'; end if; e ...

p begin HAddr <= HAddr_buf; VAddr <= VAddr_buf; H_CNT: process(clk) begin if rising_edge(clk) then if HAddr_buf = (HVisibl ...

q use IEEE.STD_LOGIC_1164.ALL; entity testB_sync_vga is end testB_sync_vga; architecture Behavioral of testB_sync_vga is compone ...

r use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.ALL; entity testB_SSD_CTRL is -- Port ( ); end testB_SSD_CTRL; architect ...

s process(clk) begin if rising_edge(clk) then if cnt = x"ff" then data(3 downto 0) <= data(3 downto 0) + x"4"; data(7 downto ...

t set_property PACKAGE_PIN R3 [get_ports {data[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {data[11]}] set_property PACKAG ...

u use IEEE.numeric_std.ALL; entity counter is Generic(number_of_bits: integer := 8); Port ( clk : in STD_LOGIC; ce : in STD_LOGI ...

v Port ( clk : in STD_LOGIC; ce : in STD_LOGIC; r : in STD_LOGIC; q : out STD_LOGIC_VECTOR (number_of_bits - 1 downto 0)); end c ...

w end process; uut: counter Generic Map (number_of_bits => 8) Port Map( clk => clk, ce => ce, r => r, q => q); en ...

x HAddr <= HAddr_reg; VAddr <= VAddr_reg; en_q <= en_q_reg; sync: Sync_VGA Port Map( clk => clk, HSync => HSync, ...

y signal clk : STD_LOGIC := '0'; signal HSync : STD_LOGIC := '0'; signal VSync : STD_LOGIC := '0'; signal R, G, B : STD_LOGIC_VE ...

"0000000110000000", "0000000110000000", "0000000110000000", "0000000110000000", z (^) Internal "0000000000000000", "000000000000 ...

"0000000000000000", "0000000000110000", "0000000001110000", "0000000011110000", aa (^) Internal "0000000110000000", "00000001100 ...